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ts3300 page 1 ? 2013 touchstone semiconductor, inc. all rights res erved. features t combines low-power boost + low dropout linear regulator (ldo) t boost regulator input voltage: 0.6v- 4.5v output voltage: 1.8v- 5.25v efficiency: up to 84% no-load supply current: 3.5a delivers >100ma at 1.8v bo from 1.2v bi shutdown control t anti-crush capability prevents input voltage collapse when powered with weak/high impedance power sources t single-inductor, discontinuous conduction mode scheme with automatic peak current adjustment t ldo adjustable ldo output voltage: 1.8v- 5v dropout voltage: 255mv @ 100ma t 16-pin, low-profile, thermally-enhanced 3mm x 3mm tqfn package applications coin cell-powered portable equipment single cell li-ion or alkaline powered equipment solar or mechanical energy harvesting wireless microphones wireless remote sensors rfid tags blood glucose meters personal health-monitoring devices description the ts3300 is a 1st-generation touchstone semi power management product that combines a high-efficiency boost regulator and a low dropout linear regulator (ldo) in one package. the boost regulator operates from a supply voltage as low as 0.6v and can deliver at least 75ma at 1.2v bi to 3v bo , an industry first. the ts3300 ldos input is connected to the output of the boost regulator, serving as a post-regulator for the boost, enabling a number of useful functions such as a buck-boost function. in power harvesting or peak load buffering applications, the ldo may post-regulate voltage buffered in a large capacitor or supercapacitor at boosts output. finally, the ldo may be operated simply as an on/off load switch. the ldo can delive r up to 100ma output current at a dropout voltage of 255mv and reduce the ripple voltage out of the boos t regulator by a factor of 3. the ts3300 s boost section includes an anti-crush tm feature to prevent the collapse of the input voltage to the boost regulator when the input is a weak (high impedance) source. if the input voltage drops below a determined voltage threshold (settable by a resistor divider), the boost regulator switching cycles are paused, effectively limiting the minimum input voltage. anti-crush tm is useful in applications where a buffer capacitor at the boosts output can service burst loads, and the input source exhibits substant ial source impedance (such as with an old battery, or at cold temperatures). the ts3300 is fully specified over the -40c to +85 c temperature range and is available in a low-profile, thermally-enhanced 16-pin 3x3mm tqfn package with an exposed back-side paddle. 0.6-4.5vin, 1.8-5.25vout, 3.5-a, low input voltage, high-efficiency boost + ldo typical application circuit the touchstone semiconductor logo and nanowatt anal og are registered trademarks of touchstone semiconductor, incorporated. i bo - ma efficiency - % 0.1 10 0 boost regulator efficiency vs load current 0.01 1 20 10 100 30 40 1.2v bi to 1.8v bo 1.2v bi to 3v bo 60 50 70 80 90 100 l: lps4018 - 103ml 0.6-4.5vin, 1.8-5.25vout, 3.5ua, low input voltage, h igh-efficiency boost + ldo
ts3300 page 2 ts3300ds r1p0 rtfds absolute maximum ratings bi to gnd ......................................... .................. -0.3v to v bo +0.1v ccp ............................................... .......................... -0.3v to +2.5v ben $ $ $ $ $ $ to gnd ............................................ ............... -0.3v to +5.75v bi fb, reg fb, bo fb to gnd ....................... ....... -0.3v to +5.75v sw en, reg en to gnd .............................. ......... -0.3v to +5.75v bo, reg out, reg in to gnd ........................ ..... -0.3v to +5.75v lsw to gnd ........................................ ................... -0.3v to +5.75v continuous power dissipation (t a = +70c) 16-pin tqfn (derate at 17.5mw/c above +70c) ..... 1398mw operating temperature range ....................... ......... -40c to +85c storage temperature range .......................... ....... -65c to +150c lead temperature (soldering, 10s) ................. .................... +300c electrical and thermal s tresses beyond those listed under absolute maximum ratings may c ause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. exposure to an y absolute maximum rating conditions for extended pe riods may affect device reliability and lifetime. package/ordering information order number part marking carrier quantity ts3300 itq16 33tp 3300i tape & reel ----- ts3300 itq16 33t tape & reel 3000 lead-free program: touchstone semiconductor supplies only lead-free pa ckaging. consult touchstone semiconductor for products specif ied with wider operating temperature ranges.
ts3300 ts3300ds r1p0 page 3 rtfds electrical characteristics v bi = 1.2v, v bo = 3v, v ben $ $ $ $ $ $ $ = low, i bo = 20ma, l = 10h, c bo = 22f unless otherwise noted. values are at t a = 25c unless otherwise noted. see note 1. parameter symbol conditions min typ max units boost regulator minimum input boost voltage v bi_min i bo = 0ma. t a =25oc 0.6 0.75 v maximum input boost voltage v bi_max guaranteed by design 4.5 v output boost voltage range v bo 1.8 5.25 v current measured at bo i b_q i bo = 0ma, v bo fb = 0.6v t a =25c 3.5 a current m easured at b i 0.07 a current measured at bo i bo = 0ma, v bo fb = 0.6v -40c < t a < + 85c 6 a current measured at bi 0.9 a efficiency eff v bi = 1.2v, v bo =1.8, i bo =30ma 84 % boost shutdown supply current i shutdown measured at bi. v ben $ $ $ $ $ $ $ = v bi v ben $ $ $ $ $ $ $ = 0v t a =25c 100 na boost feedback voltage during operation v bo fb output voltage accuracy: 4% 0.489 0.505 0.521 v boost feedback pin current i bo fb 0.1 1 na anti-crush feedback voltage v bi fb v bi 0.6v 0.363 0.392 0.425 v anti-crush feedback voltage hysteresis v bi fb_hyst 50 mv boost enable threshold v ben $ $ $ $ $ $ $ v il 0.2 v v ih v bi -0.05 v boost enable hysteresis v ben $ $ $ $ $ $ _hyst 200 mv inductor peak current i pk no load 365 ma inductor valley current i v 10 ma n-channel on resistance rds n-ch 0.27 p-channel on resistance rds p-ch 0.48
ts3300 page 4 ts3300ds r1p0 rtfds electrical characteristics v regin = v bo = 3v, v regout = 1.8v, v reg en = high, i regout = 20ma, c regout = 10f unless otherwise noted. values are at t a = 25c unless otherwise noted. see note 1. parameter symbol conditions min typ max units linear regulator dc output a ccuracy v regout 2.3 v v regin 5v 0ma i regout 20ma v reg fb = 505mv 2.5 % -40oc t a 85oc -3.5 3.5 % input voltage range v regin guaranteed by design 1.8 5.25 v output voltage range v regout 1.8 5 v input supply current i regin i regout = 0ma, v reg en = v regin 0.4 1 a line regulation v regout / v regin v regout +0.5v v regin 5v -1 1 % load regulation v regout / i regout 10ma i regout 20ma -1 1 % 0ma i regout 20ma -1.5 1.5 % drop out voltage vdo 40 mv output current limit icl 150 ma power supply rejection ratio psrr c regout = 22f i regout = 100ma f = 10hz -70 db f = 100hz -50 db f = 1khz -36 db startup time t str 1 ms linear regulator enable voltage v reg en v il (cmos logic) 0.2 x v regin v v ih (cmos logic) 0.8 xv regin v linear regulator enable hysteresis v reg en _hyst 100 mv enable pin current i reg en 10 na switch rds on r sw v sw en = high. measured from regin to regout 0.9 1.2 switch enable voltage v sw en v il (cmos logic) 0.2 x v regin v v ih (cmos logic) 0.8 xv regin v regulator feedback pin current i reg fb 0.1 1 na note 1: all devices are 100% production tested at t a = +25c and are guaranteed by characterization for t a = t min to t max , as specified.
ts3300 ts3300ds r1p0 page 5 rtfds i bo - ma efficiency - % 0.1 10 0 boost regulator efficiency vs load current 0.01 1 20 10 100 i regout - ma percent deviation - % +0.4 - 0.8 ldo output voltage accuracy vs load current - 0.2 25 50 0 75 100 150 v bi - v i bo - ma 1 120 0 boost regulator maximum output current vs v bi ( for v bo to drop 2.5%) 0.5 1.5 180 2 2.5 240 300 typical performance characteristics v bi = 1.2v, v bo = 3v, v ben $ $ $ $ $ $ = low, i bo = 0a, l = 10h (lps4018-103ml), c bo = 22f, c bi = 22f, v regin = v bo = 3v, v regout = 1.8v, i regout = 0a, c regout = 10f unless otherwise noted. values are at t a = 25c unless otherwise noted. 30 40 -1.4 -2 -2.6 -3.2 -3.8 125 1.2v bi to 1.8v bo 1.2v bi to 3v bo 60 v bo =1.8v v bo =3v 60 50 70 80 90 100 l: lps4018 - 103ml i regout - ma dropout voltage - v ldo dropout voltage vs load current 0.6 0.4 0.2 25 50 0 75 100 0 40 o c +85 o c +25 o c v regout set to 1.8v i regout - ma dropout voltage - v ldo dropout voltage vs load current 0.15 0.1 0.05 25 50 0 75 100 0 - 40 o c +85 o c +25 o c v regout set to 3v 0.2 i bo - ma inductor peak current - a 25 50 0.2 inductor peak current vs load curre nt 0 75 0.4 0.5 0.3 100 0.6 0.8 0.9 0.7 1.2v bi to 1.8v bo 1.2v bi to 3v bo 1 1.1
ts3300 page 6 ts3300ds r1p0 rtfds typical performance characteristics v bi = 1.2v, v bo = 3v, v ben $ $ $ $ $ $ = low, i bo = 0a, l = 10h (lps4018-103ml), c bo = 22f, c bi = 22f, v regin = v bo = 3v, v regout = 1.8v, i regout = 0a, c regout = 10f unless otherwise noted. values are at t a = 25c unless otherwise noted. v bo C 50mv/div 50s/div boost regulator output voltage ripple v bi = 1.2v, v bo = 1.8v, c bo = 22f, i bo = 80ma 50s/div v bo C 50mv/div boost regulator output voltage ripple v bi = 1.2v, v bo = 1.8v, c bo = 22f, i bo = 40ma 2 0s/div v bo C 50mv/div boost regulator output voltage ripple v bi = 1.2v, v bo = 1.8v, c bo = 22f, i bo = 5ma source resistance - start - up voltage - v 5 10 0.5 boost minimum start - u p voltage vs source resistance 0 15 0.7 0.8 0.6 20 25 0.9 1.1 1.2 1 30 - 40 o c +85 o c +25 o c l: 10 h (lps4018 - 103ml) i bo - ma start - up voltage - v 3 6 0. 8 boost minimum start - u p voltage vs load current 0 9 1.2 1 .4 1 12 15 1.6 1 .8 18 l: 22 h (lps4018 - 223ml) boost regulator output voltage ripple v bi = 1.2v, v bo = 3v, c bo = 22f, i bo = 5ma 50s/div v bo C 50mv/div
ts3300 ts3300ds r1p0 page 7 rtfds typical performance characteristics v bi = 1.2v, v bo = 3v, v ben $ $ $ $ $ $ = low, i bo = 0a, l = 10h (lps4018-103ml), c bo = 22f, c bi = 22f, v regin = v bo = 3v, v regout = 1.8v, i regout = 0a, c regout = 10f unless otherwise noted. values are at t a = 25c unless otherwise noted. v bo 100mv/div 200s/div boost regulator load step response v bi = 1.2v, v bo = 3v, c bo = 10f, i bo = 5ma boost regulator load step response v bi = 1.2v, v bo = 3v, c bo = 10f, i bo = 40ma 200s/div ldo load step response v bi = 1.2v, v bo = 3v, c regout = 10f, i bo = 5ma 200s/div i bo 4.17ma/div v bo 100mv/div i bo 33ma/div v regout 100mv/div i regout 4.17ma/div boost regulator output voltage ripple v bi = 1.2v, v bo = 3v, c bo = 22f, i bo = 80ma 50s/div v bo C 50mv/div 2 s/div boost regulator output voltage ripple, inductor cur rent, and lsw voltage v bi = 1.2v, v bo = 1.8v, c bo = 22f, i bo = 5ma v bo 50mv/div v lsw 1v/div i l 100ma/div l: lps4018 - 103ml ldo load step response v bi = 1.2v, v bo = 3v, c regout = 10f, i bo = 40ma 200s/div v regout 100mv/div i regout 33ma/div
ts3300 page 8 ts3300ds r1p0 rtfds typical performance characteristics v bi = 1.2v, v bo = 3v, v ben $ $ $ $ $ $ = low, i bo = 0a, l = 10h (lps4018-103ml), c bo = 22f, c bi = 22f, v regin = v bo = 3v, v regout = 1.8v, i regout = 0a, c regout = 10f unless otherwise noted. values are at t a = 25c unless otherwise noted. 2 s/div boost regulator output voltage ripple, inductor cur rent, and lsw voltage v bi = 1.2v, v bo = 3v, c bo = 22f, i bo = 40ma v bo 50mv/div v lsw 1v/div i l 500ma/div l: lps4018 - 103ml 10 0ms/div large output capacitor start - up with anti - crush at 0.9v v bi =1.2v, esr of v bi =10 , v bo =v regin =3v, v regout =1.8v, c bo =500f, c regout =10f bo 1v/div regout 1v/div i bi 50ma/div
ts3300 ts3300ds r1p0 page 9 rtfds pin functions pin name function 1 bin boost input. bypass this pin with a 22f ceramic cap acitor in close proximity to the ts3300. 2 ccp charge pump capacitor. place a 3.3nf capacitor betwee n this pin and gnd 3 ben $ $ $ $ $ $ boost enable (active low). to enable the ts3300, co nnect this to gnd. to disable the ts3300, set the voltage to greater than v bi C 50mv. 4 bi fb boost input feedback for anti-crush voltage setting. the bi fb pin voltage is 392 mv. to set the anti-crush voltage, refer to the applications information section and to figure 7. 5 fac factory use only. do not connect to gnd or vdd. leav e open. 6 sw en switch enable. when sw en is high and reg en is low , the internal fet/switch connects the ldo output to the ldo input . the internal fet has an rds on = 1.2. refer to table 1. 7 reg en ldo regulator enable. when reg en is high and sw en is low, the ldo is under normal operation. refer to table 1. 8 reg fb ldo regulator output feedback. the reg fb pin voltag e is 505mv. reg fb coupled with a voltage divider circuit sets t he ldo output voltage. refer to figure 3. 9 gnd ground. connect this pin to the analog ground plane 10 regout ldo regulator output voltage. a minimum output capa citance of 10f is recommended to be placed from this pin to gnd. to s et the ldo output voltage, use a voltage divider circuit along with th e reg fb pin as shown in figure 3. 11 regin ldo regulator input/boost output. regin should alwa ys be connected to the boost r egulator output voltage pin bo. bo is always the input to the ldo. do not apply an external supply voltage to thi s pin. 12 gnd ground. connect this pin to the analog ground plane. 13 bo fb boost output feedback. the bo fb pin voltage is 505 mv. bo fb coupled with a voltage divider circuit sets the boost regulator output voltage. refer to figure 2. 14 bo boost regulator output voltage. a minimum output ca pacitance of 10f is recommended to be placed from this pin to gnd. t o set the boost regulator output voltage, use a voltage divider circ uit along with the bo fb pin. refer to figure 2. 15 lsw coil is a low-esr, high-saturation current, shielded inductor. a 10h inductor is recommended for most applications and is to be placed from this pin to the input of the boost regulator bi. furthermore, there should exist at least an 8 % margin between the saturation current of the inducto r and the peak inductor current for a given set of operat ing conditions. 16 gnd ground. connect this pin to the analog ground plane. ep f for best electrical and thermal performance, connect exposed paddle to gnd.
ts3300 page 10 ts3300ds r1p0 rtfds block diagram theory of operation the ts3300 is a power management product that combines a high-efficiency boost regulator and a linear regulator into one package. it is the industr ys 1 st boost regulator + linear regulator where the boost regulator can operate from supply voltages as low a s 0.6v and can deliver at least 75ma at 1.2v bi and 3v bo . under no-load conditions, the boost regulator idles at 3.5a. the internal, low-dropout linear regulator is driven by the output of the boost regulator. it can deliver up to 100ma output current at a dropout voltage of 255mv and reduce the ripple voltage out of the boost regulator by a factor of 3. boost regulator at start-up, an internal low voltage oscillator in the start-up control circuitry drives the gate of the int ernal fet to charge the load capacitor. once the output voltage reaches approximately 1.1v, the main contro l circuitry starts to operate. with an adjustable peak inductor current, the ts3300 can provide up to 84% efficiency with a 1.2v bi and 3v bo . refer to figure 1. the input and output supply voltage range for the boost regulator is from 0.6v to 4.5v and 1.8v to 5.25v, respectively. figure 1: 1.2v input to 3v boost regulator output voltage and to 1.8v ldo output voltage circuit boost regulator by a factor of 3 .
ts3300 ts3300ds r1p0 page 11 rtfds the output voltage can be set via a voltage divider circuit as shown in figure 2. the output feedback (bo fb) pin is 505mv. it is recommended to use large resistor values to minimize additional current draw at the output. resistors values less than 8m are recommended. using the following equation to solve for r1 for a given r2 value, the output voltage can be set: r1= : v bo 0.505 ; r2 0.505 to set a 3v output voltage with r2 = 1.37m , r1 is calculated to be 6.77m . a 1% standard resistor value of 6.81m can be selected. this results in an output voltage of 3.02v. a shutdown ( ben $ $ $ $ $ $ ) pin is also available to shutdown the boost regulator. the boost regulator is in shutdown mode when ben $ $ $ $ $ $ is low and supply current reduces to 0.1a. ldo post-regulator the input and output supply voltage range for the ldo is from 2.3v to 5.25v and 1.8v to 5v, respectively, where the ldo input is driven by the output of the boost regulator. the output voltage ca n be set via a voltage divider circuit as shown in figure 3. the output feedback (reg fb) pin is 505mv. it is recommended to use the largest resistor values to minimize additional current draw at the output. using the following equation to solve for r3 for a given r4 value, the output voltage can be set: r3= : v regout 0.505 ; r4 0.505 to set a 1.8v output voltage with r4 = 2.61m , r3 is calculated to be 6.69m . a 1% standard resistor value of 6.81m can be selected. this results in an output voltage of 1.82v. figure 2: setting the boost output voltage with a voltage divider figure 3: setting the ldo output voltage with a voltage divider figure 4: ts3300 ldo fet/switch enabled circuit
ts3300 page 12 ts3300ds r1p0 rtfds the ldo was designed to operate in conjunction with the boost regulator where the output of the boost regulator is connected to the input to the linear regulator. the ldo can provide an output voltage based on the resistor divider circuit as shown in figure 3 or the output voltage can be set to the inp ut voltage where the internal switch/fet is fully enhanced. table 1 summarizes the settings for pins reg en and sw en. figure 4 shows the configuration where the internal switch/fet is fully enhanced (sw en =high, reg en = low) so the boost output is equal to the ldo output. the ldo can be shutdown by connecting the ref fb pin to bo when sw en = low and reg en = high. applications information inductor selection a low esr, shielded 10h inductor is recommended for most applications and provides the best compromise between efficiency and size. a low loss ferrite and low dc resistance (dcr) inductor is best for optimal efficiency. furthermore, there should exist at least an 8% margin between the saturation current of the inductor and the peak inductor current for a given set of operating conditions. table 2 provides a list of inductor manufactures. refer to the inductor peak current vs load current plot in the typical performance characteristics section. this plot shows how the inductor peak current varies with load current with a lps4018-103ml inductor from coilcraft. input and output capacitor selection for the boost regulator, a low esr ceramic input and output capacitor of at least 10 f is recommended to be placed as close as possible to the bi and bo pin . output voltage ripple can be reduced by increasing the value of the output capacitor while providing improved transient response. ceramic capacitors with x5r dielectric are recommended. for the ldo, a low esr ceramic input and output capacitor of at least 10f is recommended to be placed as close as possible to the reg out pin. refer to table 2 for a list of inductor and capacitor manufacturers. buck-boost function the ts3300 can act as a buck-boost device. for instance, if two 1.5v alkaline cells are used to pow er the ts3300, the boost output voltage (v bo ) can be set to 5v and the ldo output voltage (v regout ) can be set to 2.5v. the output voltage for the boost regulator and the ldo can be set according to figure 2 and 3, respectively. boost input anti-crush tm feature the ts3300 includes an anti-crush tm feature to prevent the collapse of the input voltage to the boo st regulator when the input is a weak (high impedance) source. if the input voltage drops below a determined voltage threshold (settable by a resistor divider), t he boost regulator switching cycles are paused, effectively limiting the minimum input voltage. anti-crush tm is useful in applications where a buffer c apacitor at the boosts output can service burst loads, and the input source exhibits substantial source impedance (such as with an old battery, or at cold temperatures). to set the anti-crush tm voltage, a feedback pin (bi fb) in conjunction with a voltage divider circui t can be implemented as shown in figure 7. the feedback pin voltage is 392mv. it is recommended to use large resistor values to minimize additional current draw at the input. sw en reg en condition function low high connect reg en pin to bo pin ldo normal o peration connect reg fb pin to bo pin ldo shutdown high low connect sw en pin to bo pin internal fet hard-o n table 1. ldo reg en and sw en settings inductors supplier website coilcraft www.coilcraft.com murata www.murata.com sumida www.sumida.com capacitors taiyo yuden www.t -yuden.com murata www.murata.com avx www.avxcorp.com tdk www.component.tdk.com table 2. inductor and capacitor manufactures
ts3300 ts3300ds r1p0 page 13 rtfds using the following equation to solve for r5 for a given r6 value, the output voltage can be set: r5= k v anticrush tm 0.392 o r6 0.392 to set a 0.8v output voltage with r6 = 1.37m , r5 is calculated to be 1.42m . a 1% standard resistor value of 1.37m can be selected. this results in an anti-crush voltage of 784mv. the anti-crush tm voltage is to be set above the minimum input voltag e specification of the ts3300. figure 5 shows a scope capture of the anti-crush tm feature in action at start-up under a heavy capacitiv e load of 500f and an input source impedance of 10. a high source impedance is typical of a weak battery source. the measurement was performed with the anti-crush tm voltage set to 0.9v. the purple, blue, and pink trace represent the input current, boost output voltage, and ldo output voltage, respectivel y. at start-up, the current rises up to 50ma and drops to approximately 30ma for approximately 40ms in order to charge the output capacitor. at this point, the voltage to the input of the ts3300 is 0.9v until th e boost output achieves regulation and in turn, the ld o output voltage achieves regulation as well. figure 6 shows a scope capture of the load step response. the measurement was performed with the anti-crush tm voltage set to 0.9v. as the output of the ldo is pulsed with a 100ma load every 100ms for 1ms as shown by the pink curve, the input voltage after a battery impedan ce of 10 drops from 1.2v to 0.9v as shown by the blue curve and the boost output voltage drops by only 160mv as shown by the yellow curve. the ts3300 quickly replenishes the 500f capacitor and the output of the boost regulat or returns to 3v. note that the ldo remains regulated and is unaffected by the load step. figure 6: using the anti-crush tm feature to maintain regulation of the boost regulator and ldo output voltage 2 ms/div load step response with anti - crush tm at 0.9v v bi =1.2v, esr of v bi =10 , v bo =v regin =3v, v regout =1.8v, c bo =500f, c regout =10f, i regout =100ma pulse bo 200mv/div i regout 83ma/div regout 200mv/div bi 500mv/div figure 7: setting the anti-crush tm voltage with a voltage divider figure 5: using the anti-crush tm feature under a heavy capacitive load (500f) and a 10 boost input source impedance at start-up 10 0ms/div large output capacitor start - up with anti - crush tm at 0.9v v bi =1.2v, esr of v bi =10 , v bo =v regin =3v, v regout =1.8v, c bo =500f, c regout =10f bo 1v/div regout 1v/div i bi 50ma/div
ts3300 page 14 touchstone semiconductor, inc. ts3300ds r1p0 630 alder drive, milpitas, ca 95035 rtfds +1 (408) 215 - 1220 www.touchstonesemi.com package outline drawing information furnished by touchstone semiconductor i s believed to be accurate and reliable. however, to uchstone semiconductor does not assume any re sponsibility for its use nor for any infringements of patents or other rights of third parties that may result from its use , and all information provided by touchstone semiconductor an d its suppliers is provided on an as is basis, with out warranty of any kind. touchstone semiconductor reserves the right to chan ge product specifications and product descriptions at any time with out any advance notice. no license is granted by implication or oth erwise under any patent or patent rights of touchst one semiconductor. touchstone semiconductor assumes no liability for applications assistance or customer product design. customers ar e responsible for their products and applications using touchstone semiconductor componen ts. to minimize the risk associated with customer pr oducts and applications, customers should provide adequate design and operat ing safeguards. trademarks and registered trademark s are the property of their respective owners. 3.00 0.05 3.00 0.05 pin 1 indicator 0.25 0.05 0.25 ref. 0.0 ? 0.05 0.75 0.05 0.10 ref. detail a 0.10 ref. 0.0 ? 0.05 0.203 ref. terminal thickness note: 1. all dimensions are in mm 2 compliant with jedec mo-220 detail a : terminal thickness for reference only no measurement purpose 1.80 0.05 1.80 0.05 1.50 ref. co.25 dap size 2x2 1.50 ref. 0.50 ref. 0.35 0.05 16 - pin tqfn33 package outline drawing (n .b., drawings are not to scale)

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